Original equipment manufacturers (OEMs) manufacture computing systems on a board using components from multiple sources. The OEMs need to test the entire board to determine if there are shorts or crossed wires (such as shorts to the high voltage source (VDD), shorts to system ground (GND), or shorts among signals). Testing the entire board with components loaded may result in difficulty determining if a test failure is a result of a component error or a board error.
Traditional board testing of connections to main memory (e.g., to dynamic random access memory (DRAM) devices or dual inline memory modules (DIMMs)) requires turning on all input/output (I/O) interface connections to perform the testing. Thus, there is traditionally a dependency problem in OEM board-level testing, because the I/O to the memory would typically not be enabled until the processor is enabled for testing, but the processor would require access to memory to perform its testing. Thus, the I/O to communicate with the memory does not get enabled until after the memory is supposed to be tested.
One traditional way to address the OEM board level testing is to require the memory devices and memory controller to come out of reset early enough to be able to perform testing for opens/shorts and lumped capacitance effects before the “booting” stage initiates. Bringing the memory subsystem out of reset early ensures that OEMs can detect board level faults, I/O connectivity issues to the memory, and any defects in memory's basic functionality before the memory reference code (MRC) commences. The early memory subsystem testing is traditionally performed with low speed (relative to the access speed of memory in active operation) testing sequences. The low speed sequences involve the sending of test codes through testing connectors to the memory components.
The platform testing with early exit from reset can add significant time to the testing procedure and violate testing goals for the OEMs. With an increased focus on power management in emerging products, platforms have incorporated elaborate embedded power gating and reset control mechanisms to meet the platform power requirements. With the platform gating and reset control, the testing requires external customers to complete the reset sequence for checking the I/O connectivity to the memory. Such a requirement on the external customer violates OEM requirements for testing the on-board memory I/O with minimal reset. Additionally, it increases internal test times for high volume manufacturing (HVM) up to several seconds, resulting in increased test time cost.
Descriptions of certain details and implementations follow, including non-limiting descriptions of the figures, which may depict some or all examples, and well as other potential implementations.